首页 > IT职业 > IT生活 > RK281x芯片怎么样?RK281x处理器参数介绍


IT生活 作者:SZX511 时间:2019-06-17 15:09:43 0 删除 编辑


RK281x可以通过软件和专用协处理器支持对诸如H.264/RMVB/MPEG-4/AVS/VC1/MPEG-2之类的各种类型的视频标准的解码和编码。特别是视频的最高性能对于H.264@1280x720格式的视频,代码将达到流畅的重播。RK281x还提供了强大的图形/图像能力与嵌入式GPU。通过提供一套完整的外围接口, RK281x 可以支持非常灵活的应用程序,包括SDRAM/Mobile SDRAM/DDRII/Mobile DDR、NOR、Nand Flash、LCDC、传感器、USB OTG 2.0/USB主机1.0、SD/MMC/SDIO、Wi-Fi、高速ADC、I2C、I2S,UART,SPI,PWM等。

System Operation
Dual Core Architecture (ARM9 + DSP) , including hardware accelerator
Support system boot sequentially from ARM to DSP
Support address remap function
For two cores, all modules have unified address space
Selectable JTAG debug method
--ARM9 debug only (default)
--DSP debug only

--ARM9+DSP dual core debug

Selectable CPU booting method
Boot from NOR Flash
Boot from Nand Flash
Boot from SPI nor flash
Boot from UART device

Boot from Host interface

Memory Organization
-- Internal memory space for ARM processor
-- Internal 16KB SRAM for ARM9 ICache
-- Internal 16KB SRAM for ARM9 DCache
-- Internal 8KB SRAM for ARM9 ITCM

-- Internal 16KB SRAM for ARM9 DTCM

Internal memory space for DSP processor
-- Internal 96KB SRAM for DSP Instruction L1 Memory
(also config as 32KB Memory+32KB ICache by software, another 32KB is switched by software)
-- Internal 64KB SRAM for DSP Data L1 Memory
-- Internal 48KB SRAM for DSP Instruction L2 Memory

-- Internal 32KB SRAM for DSP Data L2 Memory

Embedded 8KB ROM for CPU Boot
Embedded 4KB SRAM for communication between two cores

Embedded 48KB SRAM for share among CPU,DSP and LCDC rotator

RISC architecture with 32bit ARM and 16bit Thumb instruction sets
Include efficient execution of Java byte codes
Built-in MMU to provide flexible memory management needed by many mainstream OS
Harvard cached architecture , separate ICache and DCache
Separate instruction and data TCM interfaces
Separate instruction and data AHB bus interface

Support ARM debug architecture

Based on VLIW instructions with SIMD concepts , reach high level of parallelism and high code density
Support 16bits and 32bits variable instruction sets
Based on a load/store architecture, have two load-store units
Support Nine-stage pipeline

Built-in two 16x16bit MAC units

Communication between two cores
Support share memory and interactive interrupt method to complete communication
Processor Interface Unit (PIU)
Built-in three Command/reply protocols registers and three Semaphore registers to accessed by two cores

Support three semaphore-related interrupts and one command-reply-related interrupt between two cores

Graphics hardware accellerator (GPU)
3D feature
Four times and 16 times Full Scene Anti-Aliasing (FSAA).
Lines, squares, triangles and points.
Flat and Gouraud shading.
Perspective correct texturing.
Point sampling, bilinear, and trilinear filtering.
Programmable mipmap level-of-detail biasing.
Multitexturing, with three textures.
Dot3 bump mapping.
Alpha blending.
Stencil buffering.
Point sprites.

4-bit per texel texture compression, Ericsson Texture Compression (ETC)

2D features
Lines, squares, triangles and points
Arbitrary rotation and scaling
Alpha blending

Multitexture BitBLT

External Memory Interface
Support SDRAM/Mobile SDRAM/DDRII/Mobile DDR separately
Support special SDRAM controller for high-performance video data transfer
Support Nor Flash/Nand Flash/SD/MMC/SDIO interface, Nor Flash interface is only available when use SDRAM or Mobile SDRAM
Static/SDRAM Memory controller
--Dynamic memory interface support , including SDR-SDRAM and Mobile SDRAM
--Asynchronous static memory device support including SRAM, ROM and Nor Flash with or without --asynchronous page mode
--Support 2 chip selects for (Mobile) SDRAM and 2 chip selects for static memory
--Support 16bits or 32bits width data bus (Mobile) SDRAM and 8/16 bits
--data bus static memory, it is programmable.
--Support industrial standard (Mobile) SDRAM with a maximum of 256MB of address space per chip select
--4Mbytes access space per static memory support
--Support (Mobile) SDRAM and Static Memory power-down mode
--Support (Mobile) SDRAM self-refresh mode

--Programmable arbitration priority for 6 slave data ports

DDRII/Mobile DDR Memory controller
Programmable select for DDRII or Mobile DDR function
Fully pipelined command, read and write data interface
Advanced bank look-ahead features for high memory throughput
Support one slave port for register set and 6 slave ports for data access
Separate asynchronous FIFOs for every slave ports to support different frequency between AHB bus and DDR controller, and improve utility for bandwidth

Support 32bit/16bit data width

Support 2 chip selects , with a maximum of 256MB of address space per chip select

DDRII data rate is 533M x 32bits , Mobile DDR data rate is 400M x 32bits

Customized SDRAM controller for video
Support 32bit SDRAM data width
Special mechanism to improve little-block data transfer efficiency for video, especially when use together with MCDMA

Support one slave for register set and six data slave ports

Nand Flash controller
Standard AMBA2.0 Slave interface
Support 8 chip selects for nand flash
Only support 8bit data width
Flexible CPU interface support
Embedded 2x1KB size buffer for DMA mode to improve performace
512B、2KB、4KB page size support
Support hardware 24bit ECC
Support LBA nand

Support FF code auto correct process

SD/MMC controller
Two Embedded SD/MMC Controllers, one is 4bit data bus , another is 8bit data bus
Compliant with SD Memory/SDIO with 1bit and 4bit data bus
Compliant with MMC V3.3 and V4.0 with 1/4/8bit data bus
Support combined single 32x32bits FIFO for both transmit and receive operations
Support FIFO over-run and under-run prevention by stopping card clock
Variable SD/MMC card clock rate 0 – 52 MHz which depends on AHB clock frequency
Controllable SD/MMC card clock to save power consumption
Support card detection and initialization , and write protection
Support transfer block size of 1 to 65365Bytes

DMA based or Interrupt based operation

VIDEO/Image interface
Sensor controller
Embedded DMA function
Support 24MHz 、48MHz、27MHz clock input
Support CCIR656 PAL/NTSC input
Support YUYV and UYVY format input
Support YUV 4:2:2 and YUV 4:2:0 format output
Programmable Hsync and Vsync porality
Support 10bit or 12bit raw data input
Support sensor bypass to LCDC interface

Support 8 MegaPixels

LCD controller
Embedded DMA function
Programmable transfer mode to meet different bus bandwidth and transfer efficiency.
Support two window with scale function   
YUV422/YUV420/RGB565/RGB888 input format are supported in window0
RGB565/RGB888 input format and 4 areas are supported in window1
Support virtual display
Built-in scaler engine from 1/8 to 8
Support 16 level alpha blending and transparent operation.
Support Blank/Black Function
Support LCD Pannel resolution up to 1280x720
Compatible with MCU pannel
Compatible with 8/16/18/24bits RGB Delta/no-Delta Pannel
Compatible with 8/16/18/24bits RGB Series/Parallel Output
Support Interlace and Progressive Output
Support hardware cursor
Support rotation display
Support video dither operation
Support Interlace to progressive change for MPEG-2
Support LCDC interface bypass from Host interface or VIP interface


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